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19-2412; Rev 0; 4/02
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
General Description
The MAX1198 is a 3.3V, dual, 8-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1198 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumentation, and digital communications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 264mW, while delivering a typical signal-to-noise and distortion (SINAD) of 48.1dB at an input frequency of 50MHz and a sampling rate of 100Msps. The T/H-driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with singleended inputs. In addition to low operating power, the MAX1198 features a 3.2mA sleep mode, as well as a 0.15A power-down mode to conserve power during idle periods. An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range. The MAX1198 features parallel, CMOS-compatible threestate outputs. The digital output format can be set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing with various logic families. The MAX1198 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40C to +85C) temperature range. Pin-compatible lower speed versions of the MAX1198 are also available. Refer to the MAX1195 data sheet for 40Msps and the MAX1197 data sheet for 60Msps. In addition to these speed grades, this family includes a multiplexed output version (MAX1196, 40Msps), for which digital data is presented time interleaved and on a single, parallel 8-bit output port. For a 10-bit, pin-compatible upgrade, refer to the MAX1180 data sheet. With the N.C. pins of the MAX1198 internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX1180. o Single 2.7V to 3.6V Operation o Excellent Dynamic Performance 48.1dB/47.6dB SINAD at fIN = 50MHz/200MHz 66dBc/61.5dBc SFDR at fIN = 50MHz/200MHz o -72dB Interchannel Crosstalk at fIN = 50MHz o Low Power 264mW (Normal Operation) 10.6mW (Sleep Mode) 0.5W (Shutdown Mode) o 0.05dB Gain and 0.1 Phase Matching o Wide 1VP-P Differential Analog Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o User-Selectable Output Format--Two's Complement or Offset Binary o Pin-Compatible 8-Bit and 10-Bit Upgrades Available
Features
MAX1198
Ordering Information
PART MAX1198ECM TEMP RANGE -40C to +85C PIN-PACKAGE 48 TQFP-EP*
*EP = Exposed paddle Functional Diagram and Pin Compatible Upgrades table appear at end of data sheet.
Pin Configuration
REFN REFP REFIN REFOUT D7A D6A D5A D4A D3A D2A D1A D0A
48 47 46 45 44 43 42 41 40 39 38
COM VDD GND INA+ INAVDD GND INBINB+ GND VDD CLK
37
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31
N.C. N.C. OGND OVDD OVDD OGND N.C. N.C. D0B D1B D2B D3B
Applications
Baseband I/Q Sampling Multichannel IF Sampling Ultrasound and Medical Imaging Battery-Powered Instrumentation WLAN, WWAN, WLL, MMDS Modems Set-Top Boxes VSAT Terminals
MAX1198
30 29 28 27 26 25
VDD VDD GND
________________________________________________________________ Maxim Integrated Products
T/B SLEEP PD OE D7B D6B D5B D4B
GND
TQFP-EP
1
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND .................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D7A-D0A, D7B-D0B to OGND .............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 12.5mW/C above +70C).........1000mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 2.5V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Gain Temperature Coefficient ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 100MHz, 4096-point FFT) fINA or B = 7.5MHz at -1dB FS Signal-to-Noise Ratio SNR fINA or B = 20MHz at -1dB FS fINA or B = 50MHz at -1dB FS fINA or B = 115.1MHz at -1dB FS 47.0 48.5 48.3 48.3 48.1 dB fCLK 100 5 MHz Clock Cycles VDIFF VCM RIN CIN Switched capacitor load Differential or single-ended inputs 1.0 VDD / 2 0.2 57 5 V V k pF 100 INL DNL fIN = 7.5MHz (Note 1) fIN = 7.5MHz, no missing codes guaranteed (Note 1) 8 0.3 0.2 1 1 4 4 Bits LSB LSB %FS %FS ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.5V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS fINA or B = 7.5MHz at -1dB FS Signal-to-Noise and Distortion SINAD fINA or B = 20MHz at -1dB FS fINA or B = 50MHz at -1dB FS fINA or B = 115.1MHz at -1dB FS fINA or B = 7.5MHz at -1dB FS Spurious-Free Dynamic Range SFDR fINA or B = 20MHz at -1dB FS fINA or B = 50MHz at -1dB FS fINA or B = 115.1MHz at -1dB FS fINA or B = 7.5MHz at -1dB FS Third-Harmonic Distortion HD3 fINA or B = 20MHz at -1dB FS fINA or B = 50MHz at -1dB FS fINA or B = 115.1MHz at -1dB FS Intermodulation Distortion (First Five Odd-Order IMDs) Third-Order Intermodulation Distortion IMD fIN1(A or B) = 1.989MHz at -7dB FS fIN2(A or B) = 2.038MHz at -7dB FS (Note 2) fIN1(A or B) = 1.989MHz at -7dB FS fIN2(A or B) = 2.038MHz at -7dB FS (Note 2) fINA or B = 7.5MHz at -1dB FS Total Harmonic Distortion (First Four Harmonics) Small-Signal Bandwidth Full-Power Bandwidth Gain Flatness (12MHz Spacing) Aperture Delay Aperture Jitter Overdrive Recovery Time tAD tAJ 1dB SNR degradation at Nyquist For 1.5 x full-scale input FPBW THD fINA or B = 20MHz at -1dB FS fINA or B = 50MHz at -1dB FS fINA or B = 115.1MHz at -1dB FS Input at -20dB FS, differential inputs Input at -1dB FS, differential inputs fIN1(A or B) = 106MHz at -1dB FS fIN2(A or B) = 118MHz at -1dB FS (Note 3) 60 46.5 MIN TYP 48.3 48.2 48.1 48 67 67 66 65 -67 -67 -67 -66 -69.5 dBc dBc dBc dB MAX UNITS
MAX1198
IM3
-80 -66 -67 -64 -58 500 400 0.05 1 2 2 2.048 3% 2.162 1.138 VDD / 2 0.1 -57
dBc
dBc
MHz MHz dB ns psRMS ns
INTERNAL REFERENCE (REFIN = REFOUT through 10k resistor; REFP, REFN, and COM levels are generated internally.) Reference Output Voltage Positive Reference Output Voltage Negative Reference Output Voltage Common-Mode Level VREFOUT VREFP VREFN VCOM (Note 4) (Note 5) (Note 5) (Note 5) V V V V
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3
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.5V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Differential Reference Output Voltage Range Reference Temperature Coefficient SYMBOL VREF TCREF CONDITIONS VREF = VREFP - VREFN MIN TYP 1.024 3% 100 MAX UNITS V ppm/C
BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) Positive Reference Output Voltage Negative Reference Output Voltage Common-Mode Level Differential Reference Output Voltage Range REFIN Resistance Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current VREFP VREFN VCOM VREF RREFIN ISOURCE ISINK ISOURCE ISINK RREFP, RREFN CIN VREF VCOM VREFP VREFN VREF = VREFP - VREFN Measured between REFP, COM, REFN, and COM (Note 5) (Note 5) (Note 5) VREF = VREFP - VREFN 2.162 1.138 VDD / 2 0.1 1.024 2% >50 5 -250 250 -5 V V V V M mA A A mA
UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance REFP, REFN, COM Input Capacitance Differential Reference Input Voltage Range COM Input Voltage Range REFP Input Voltage REFN Input Voltage 4 15 1.024 10% VDD / 2 5% VCOM + VREF / 2 VCOM VREF / 2 0.8 x VDD 0.8 x OVDD k pF V V V V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) CLK Input High Threshold VIH PD, OE, SLEEP, T/B
V
4
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.5V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER SYMBOL CLK Input Low Threshold VIL PD, OE, SLEEP, T/B Input Hysteresis Input Leakage Input Capacitance Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range VDD OVDD CL = 15pF Operating, fINA & B = 20MHz at -1dB FS applied to both channels Analog Supply Current IVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, fINA & B = 20MHz at -1dB FS applied to both channels (Note 6) Output Supply Current IOVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, fINA & B = 20MHz at -1dB FS applied to both channels Analog Power Dissipation PDISS Sleep mode Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection TIMING CHARACTERISTICS CLK Rise to Output Data Valid Time OE Fall to Output Enable Time OE Rise to Output Disable Time CLK Pulse Width High CLK Pulse Width Low tDO tENABLE tDISABLE tCH tCL Clock period: 10ns (Note 7) Clock period: 10ns (Note 7) CL = 20pF (Notes 1, 7) 6 5 5 5 0.5 5 0.5 8.25 ns ns ns ns ns PSRR Offset, VDD 5% Gain, VDD 5% 2.7 1.7 3.3 2.5 80 3.2 0.15 11.5 2 2 264 10.6 0.5 3 3 66 W mV/V 10 314 20 A mA A 3.6 3.6 95 V V mA VHYST IIH IIL CIN VOL VOH ILEAK COUT ISINK = -200A ISOURCE = 200A OE = OVDD OE = OVDD 5 OVDD 0.2 10 VIH = VDD = OVDD VIL = 0 5 0.2 0.15 20 20 CONDITIONS MIN TYP MAX 0.2 x VDD 0.2 x OVDD UNITS
MAX1198
V
V A pF V V A pF
DIGITAL OUTPUTS ( D7A-D0A, D7B-D0B)
mW
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5
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.5V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Wake-Up Time SYMBOL tWAKE CONDITIONS Wake up from sleep mode Wake up from shutdown mode (Note 11) fINA or B = 20MHz at -1dB FS (Note 8) fINA or B = 20MHz at -1dB FS (Note 9) fINA or B = 20MHz at -1dB FS (Note 10) MIN TYP 1 20 -72 0.05 0.1 MAX UNITS s
CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching dB dB Degrees
Note 1: Guaranteed by design. Not subject to production testing. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power. Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two applied input signals with the same magnitude (peak-to-peak) at fIN1 and fIN2. Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1F (min) and 2.2F (typ) capacitor. Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1F (min) and 2.2F (typ) capacitor. Note 6: Typical analog output current at fINA & B = 20MHz. For digital output currents vs. analog input frequency, see Typical Operating Characteristics. Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock level to 50% of the data output level. Note 8: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level. Crosstalk is measured by calculating the power ratio of the fundamental of each channel's FFT. Note 9: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the fundamental of the calculated FFT. Note 10: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test. Note 11: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.
6
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 100MHz, CL 10pF, TA = +25C, unless otherwise noted.)
FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1198 toc01
MAX1198
FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1198 toc02
FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 fINB HD2 HD3 fINA fCLK = 100.050607MHz fINA = 114.9629350MHz fINB = 99.5010126MHz AIN = -1dB FS COHERENT SAMPLING
MAX1198 toc03
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 0 5 fINB HD2 HD3 fINA fCLK = 100.050607MHz fINA = 19.8708908MHz fINB = 7.5355498MHz AIN = -1dB FS COHERENT SAMPLING
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 HD2 fINB fCLK = 100.050607MHz fINA = 49.7443997MHz fINB = 19.8708908MHz AIN = -1dB FS COHERENT SAMPLING fINA HD3
0
10 15 20 25 30 35 40 45 50 ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1198 toc04
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1198 toc05
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
CHB 48 CHA SNR (dB) 46
MAX1198 toc06
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 0 fIN1 fIN2 fCLK = 100.007936MHz fIN1 = 1.989904MHz fIN2 = 2.038736MHz AIN = -7dB FS COHERENT SAMPLING
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90
fCLK = 100.007936MHz fIN1 = 10.022768MHz fIN2 = 10.047184MHz AIN = -7dB FS COHERENT SAMPLING fIN1
50
fIN2
44
42
40 7 8 9 10 11 12 13 0 40 80 120 160 200 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1198 toc07
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1198 toc08
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX1198 toc09
50 CHA 48 CHB
-40
80 CHA
-48
72
THD (dBc)
SNR (dB)
46
-56
SFDR (dBc)
CHB
64 CHB 56
44
-64 CHA
42
-72
48
40 0 40 80 120 160 200 ANALOG INPUT FREQUENCY (MHz)
-80 0 40 80 120 160 200 ANALOG INPUT FREQUENCY (MHz)
40 0 40 80 120 160 200 ANALOG INPUT FREQUENCY (MHz)
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7
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 100MHz, CL 10pF, TA = +25C, unless otherwise noted.)
SNR/SINAD, THD/SFDR vs. TEMPERATURE
MAX1198 toc10
FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL
MAX1198 toc11
SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL
VIN = 100mVP-P 1 0 GAIN (dB) -1 -2 -3 -4
MAX1198 toc12
90 fIN = 19.87089082MHz SNR/SINAD, THD/SFDR (dB, dBc) 80 SFDR 70 60 SNR 50 40 30 -40 -15 10 35 60 SINAD
1 0 -1 GAIN (dB) -2 -3 -4 -5
2
THD
85
1
10
100
1000
1
10
100
1000
TEMPERATURE (C)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 19.87089082MHz)
MAX1198 toc13
SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 19.87089082MHz)
MAX1198 toc14
TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 19.87089082MHz)
MAX1198 toc15
55 50 45
55 50 45 SINAD (dB)
-45 -50 -55 THD (dBc) -60 -65 -70 -75
SNR (dB)
40 35 30 25 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS)
40 35 30 25 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS)
-20
-16
-12
-8
-4
0
INPUT POWER (dB FS)
SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 19.87089082MHz)
MAX1198 toc16
INTEGRAL NONLINEARITY (262144-POINT DATA RECORD)
MAX1198 toc17
DIFFERENTIAL NONLINEARITY (262144-POINT DATA RECORD)
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
MAX1198 toc18
75 70 65 SFDR (dBc) 60 55 50 45 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS)
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 98
0.5
128 160 192 224 256
0
32
64
98
128 160 192 224 256
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
8
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -1dB FS, fCLK = 100MHz, CL 10pF, TA = +25C, unless otherwise noted.)
GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE VREFIN = 2.048V
MAX1198 toc19
MAX1198
OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE VREFIN = 2.048V
MAX1198 toc20
SNR/SINAD, THD/SFDR vs. SAMPLING SPEED
SFDR fIN = 19.87089082MHz
MAX1198 toc21
0.5
0.8
80 SNR/SINAD, THD/SFDR (dB, dBc)
CHB 0.3 GAIN ERROR (%FS)
OFFSET ERROR (%FS)
0.3
72
CHA
64 THD 56 SNR
0.1
CHA
-0.2
-0.1
-0.7 CHB
48 SINAD 40
-0.3 -40 -15 10 35 60 85 TEMPERATURE (C)
-1.2 -40 -15 10 35 60 85 TEMPERATURE (C)
0
20
40
60
80
100
120
SAMPLING SPEED (Msps)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX1198 toc22
DIGITAL SUPPLY CURRENT vs. ANALOG INPUT FREQUENCY
MAX1198 toc23
SNR/SINAD, THD/SFDR vs. CLOCK DUTY CYCLE
SFDR SNR/SINAD, THD/SFDR (dB, dBc) 70
MAX1198 toc24
90
20
80
86
16
IVDD (mA)
82
IOVDD (mA)
12
60
THD SNR
78
8
50 SINAD fIN = 19.87089082MHz
74
4
40
70 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 10 20 30 40 50 ANALOG INPUT FREQUENCY (MHz)
30 40 44 48 52 56 60 CLOCK DUTY CYCLE (%)
INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX1198 toc25
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1198 toc26
2.0430 2.0425 2.0420 VREFOUT (V)
2.0500
2.0460 VREFOUT (V)
2.0420
2.0415 2.0410 2.0405 2.0400 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
2.0380
2.0340
2.0300 -40 -15 10 35 60 85 TEMPERATURE (C)
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9
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
Pin Description
PIN 1 2, 6, 11, 14, 15 3, 7, 10, 13, 16 4 5 8 9 12 17 NAME COM VDD GND INA+ INAINBINB+ CLK T/B FUNCTION Common-Mode Voltage I/O. Bypass to GND with a 0.1F capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2F in parallel with 0.1F. Analog Ground Channel A Positive Analog Input. For single-ended operation connect signal source to INA+. Channel A Negative Analog Input. For single-ended operation connect INA- to COM. Channel B Negative Analog Input. For single-ended operation connect INB- to COM. Channel B Positive Analog Input. For single-ended operation connect signal source to INB+. Converter Clock Input T/B Selects the ADC Digital Output Format High: Two's complement Low: Straight offset binary Sleep Mode Input High: Disables both quantizers, but leaves the reference bias circuit active Low: Normal operation Active-High Power-Down Input High: Power-down mode Low: Normal operation Active-Low Output Enable Input High: Digital outputs disabled Low: Digital outputs enabled Three-State Digital Output, Bit 7 (MSB), Channel B Three-State Digital Output, Bit 6, Channel B Three-State Digital Output, Bit 5, Channel B Three-State Digital Output, Bit 4, Channel B Three-State Digital Output, Bit 3, Channel B Three-State Digital Output, Bit 2, Channel B Three-State Digital Output, Bit 1, Channel B Three-State Digital Output, Bit 0, Channel B No Connection Output Driver Ground Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2F in parallel with 0.1F. Three-State Digital Output, Bit 0, Channel A Three-State Digital Output, Bit 1, Channel A Three-State Digital Output, Bit 2, Channel A Three-State Digital Output, Bit 3, Channel A Three-State Digital Output, Bit 4, Channel A
18
SLEEP
19
PD
20 21 22 23 24 25 26 27 28 29, 30, 35, 36 31, 34 32, 33 37 38 39 40 41
OE D7B D6B D5B D4B D3B D2B D1B D0B N.C. OGND OVDD D0A D1A D2A D3A D4A
10
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
Pin Description (continued)
PIN 42 43 44 45 46 47 48 NAME D5A D6A D7A REFOUT REFIN REFP REFN Three-State Digital Output, Bit 5, Channel A Three-State Digital Output, Bit 6, Channel A Three-State Digital Output, Bit 7 (MSB), Channel A Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistordivider. Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a >0.1F capacitor. Positive Reference I/O. Conversion range is (VREFP - VREFN). Bypass to GND with a >0.1F capacitor. Negative Reference I/O. Conversion range is (VREFP - VREFN). Bypass to GND with a >0.1F capacitor. FUNCTION
MAX1198
2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 6 STAGE 7 STAGE 1 STAGE 2 STAGE 6
2-BIT FLASH ADC STAGE 7
DIGITAL ALIGNMENT LOGIC T/H 8 D7A-D0A T/H
DIGITAL ALIGNMENT LOGIC 8 D7B-D0B
VINA
VINB
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
Figure 1. Pipelined Architecture--Stage Blocks
Detailed Description
The MAX1198 uses a seven-stage, fully differential pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles. Flash ADCs convert the held input voltages into a digital code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all seven stages.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the input T/H circuits in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
INTERNAL BIAS S2a C1a S4a INA+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM HOLD INTERNAL BIAS S2a C1a S4a INB+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM OUT TRACK HOLD TRACK CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS OUT COM S5a S3a
INA-
COM S5a S3a
INB-
MAX1198
Figure 2. MAX1198 T/H Amplifiers
are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1 sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on
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capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1198 to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+ and INA-, INB-) can be driven either differentially or single ended.
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
5-CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6
ANALOG INPUT tAD
CLOCK INPUT tDO DATA OUTPUT D7A-D0A N-6 N-5 N-4 tCH N-3
tCL N-2 N-1 N N+1
DATA OUTPUT D7B-D0B
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
Figure 3. System Timing Diagram
Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to mid supply (VDD/2) for optimum performance.
Analog Inputs and Reference Configurations
The full-scale range of the MAX1198 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. The MAX1198 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10k) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise-filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN are outputs. REFOUT can be left open or connected to REFIN through a >10k resistor.
In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high-impedance inputs and can be driven through separate, external reference sources. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section.
Clock Input (CLK)
The MAX1198's CLK input accepts a CMOS-compatible clock signal. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: SNR = 20 x log 1 2 x x f IN x t AJ
where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines.
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
OE
Table 1. MAX1198 Output Codes For Differential Inputs
tENABLE tDISABLE HIGH-Z HIGH-Z
OUTPUT D7A-D0A
VALID DATA
DIFFERENTIAL DIFFERENTIAL INPUT INPUT VOLTAGE* VREF x 255/256 VREF x 1/256 +Full Scale - 1LSB +1LSB Bipolar Zero -1LSB -Full Scale + 1LSB -Full Scale
STRAIGHT TWO'S OFFSET COMPLEMENT BINARY T/B = 0 T/B = 1 1111 1111 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000 0111 1111 0000 0001 0000 0000 1111 1111 1000 0001 1000 0000
OUTPUT D7B-D0B
HIGH-Z
VALID DATA
HIGH-Z
Figure 4. Output Timing Diagram
0 -VREF x 1/256 -VREF x 255/256 -VREF x 256/256
The MAX1198 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics table.
System Timing Requirements
Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1198 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 3 also determines the relationship between the input clock parameters and the valid output data on channels A and B.
*VREF = VREFP - VREFN
Power-Down and Sleep Modes
The MAX1198 offers two power-save modes--sleep mode (SLEEP) and full power-down (PD) mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 3.2mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to power-down. Pulling OE high forces the digital outputs into a high-impedance state.
Digital Output Data (D0A/B-D7A/B), Output Data Format Selection (T/B), Output Enable (OE)
All digital outputs, D0A-D7A (channel A) and D0B-D7B (channel B), are TTL/CMOS-logic compatible. There is a five-clock-cycle latency between any particular sample and its corresponding output data. The output coding can either be straight offset binary or two's complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two's complement output coding. The capacitive load on the digital outputs D0A-D7A and D0B-D7B should be kept as low as possible (<15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1198, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1198, small-series resistors (e.g., 100) may be added to the digital output paths close to the MAX1198. Figure 4 displays the timing relationship between output enable and data output valid, as well as powerdown/wakeup and data output valid.
Applications Information
Figure 5 depicts a typical application circuit containing two single-ended-to-differential converters. The internal reference provides a VDD/2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per amplifier suppresses some of the wideband noise associated with high-speed op amps. The user can select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 5, a RISO of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small filter capacitor.
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1198 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer can be selected to reduce the drive
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
+5V
0.1F LOWPASS FILTER MAX4108 0.1F INARIS0 50 CIN 22pF
300
-5V
0.1F
600 300 +5V 0.1F 0.1F INPUT 0.1F MAX4108 300 0.1F MAX4108 INA+ RIS0 50 0.1F CIN 22pF LOWPASS FILTER 600 +5V 600 COM
-5V
300 -5V
300 300 +5V 600
MAX1198
0.1F LOWPASS FILTER MAX4108 0.1F INBRIS0 50 CIN 22pF
300
-5V
0.1F
+5V 300 0.1F INPUT MAX4108 300 0.1F 0.1F
600
600
+5V 600 0.1F MAX4108 RIS0 50 -5V 0.1F CIN 22pF LOWPASS FILTER INB+
-5V
300
300 300 600
Figure 5. Typical Application for Single-Ended-to-Differential Conversion ______________________________________________________________________________________ 15
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
25 INA+ 22pF
VIN 0.1F 1k RISO 50 INA+ 100 1k CIN 22pF COM REFN 0.1F RISO 50 INACIN 22pF REFP REFP
0.1F VIN N.C. 1 2 3 T1 6 5 4 2.2F 0.1F
MAX4108
COM
MINICIRCUITS TT1-6-KK81 25 INA22pF MAX1198 25 INB+ 22pF 0.1F VIN N.C. 1 2 3 T1 6 5 4 2.2F 0.1F
REFN 0.1F VIN 0.1F 1k RISO 50 100
MAX1198
MAX4108
100 1k
INB+ CIN 22pF
MINICIRCUITS TT1-6-KK81 25 INB22pF
RISO 50 INBCIN 22pF
100
Figure 6. Transformer-Coupled Input Drive
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive
requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. In general, the MAX1198 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode.
Buffered External Reference Drives Multiple ADCs
Multiple-converter systems based on the MAX1198 are well suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source. A precision bandgap reference like the MAX6062 generates an external DC level of 2.048V (Figure 8), and exhibits a noise-voltage density of 150nV/Hz. Its output passes through a 1-pole lowpass filter (with 10Hz cutoff frequency) to the MAX4250, which buffers the reference before its output is applied to a second 10Hz lowpass filter. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level. The passive 10Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision ADC operation.
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
3.3V 0.1F 0.1F 1 0.1F MAX6062 2 16.2k 3 5 MAX4250 4 3 10Hz LOWPASS FILTER 2 1 162 100F 0.1F 0.1F 0.1F 10Hz LOWPASS FILTER 3.3V 2.048V N.C. 29 31 32 1 2 REFOUT REFIN REFP REFN COM
N=1 MAX1198
1F
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.
0.1F
2.2F 10V
N.C.
29 31
REFOUT REFIN REFP REFN COM
0.1F
32 1 2
N = 1000 MAX1198
0.1F 0.1F 0.1F
Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
Unbuffered External Reference Drives Multiple ADCs
Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage-divider, the MAX6066 generates a DC level of 2.500V. The buffered outputs of this divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy that depends on the tolerance of the divider resistors. These three voltages are buffered by the MAX4252, which provides low noise and low DC offset. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3nV/Hz. The 2.0V and 1.0V reference voltages set the differential full-scale range of the associated ADCs at 2VP-P. The 2.0V and 1.0V buffers drive the ADC's internal ladder resistances between them.
Note that the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications that require more than 32 matched ADCs, a voltage reference and divider string common to all converters is highly recommended.
Typical QAM Demodulation Application
A frequently used modulation technique in digital communications applications is quadrature amplitude modulation (QAM). Typically found in spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent upconversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 phase
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
3.3V 0.1F 1 2.0V MAX6066 2 21.5k 3 4 1/4 MAX4252 1 2 3 21.5k 1.5V 5 4 1/4 MAX4252 7 6 1F 21.5k 3.3V 0.1F 11 10F 6V 1.47k 3.3V 10 4 1/4 MAX4252 8 21.5k MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 9 11 21.5k 10F 6V 1.47k 330F 6V N.C. 29 31 32 1 2 REFOUT REFIN REFP REFN COM 47 1.0V AT -8mA 330F 6V 0.1F 2.2F 10V 47 11 10F 6V 1.47k 3.3V 1.5V AT 0mA 330F 6V 0.1F 0.1F 0.1F 47 2 COM 3.3V 2.0V AT 8mA N.C. 29 31 32 1
REFOUT REFIN REFP REFN
N=1 MAX1198
1.0V
N = 32 MAX1198
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.
0.1F 0.1F 0.1F
Figure 9. External Unbuffered Reference Drive with MAX4252 and MAX6066
shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into its I and Q components, essentially representing the modulation process reversed. Figure 10 displays the demodulation process performed in the analog domain, using the dual matched 3.3V, 8-bit ADC MAX1198 and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1198, the mixed down-signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters, which remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.
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Grounding, Bypassing, and Board Layout
The MAX1198 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1F ceramic capacitors and a 2.2F bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
MAX2451
INA+ INA0 90
MAX1198 INB+ INB-
DSP POSTPROCESSING
DOWNCONVERTER /8
Figure 10. Typical QAM Application Using the MAX1198
Static Parameter Definitions
CLK
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1198 are measured using the best-straight-line-fit method.
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
Differential Nonlinearity
T/H TRACK HOLD TRACK
Figure 11. T/H Aperture Timing
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 turns.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 11).
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N-bits): SNRdB[max] = 6.02dB N + 1.76dB
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. THD = 20 x log V22 + V32 + V4 2 + V52 V1
Signal-to-Noise Plus Distortion
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
Effective Number of Bits
Effective number of bits (ENOB) specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = SINAD - 1.76 6.02
Intermodulation Distortion
The two-tone intermodulation distortion (IMD) is the ratio expressed in decibels of either input tone to the worst third-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale and their envelope is at -1dB full scale.
Total Harmonic Distortion
THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as:
Chip Information
TRANSISTOR COUNT: 11,601 PROCESS: CMOS
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
Functional Diagram
VDD GND INA+ T/H INAADC DEC 8 OUTPUT DRIVERS 8 D7A-D0A OGND OVDD
MAX1198
CLK
CONTROL OE
INB+ T/H INBADC DEC
8
OUTPUT DRIVERS
8 D7B-D0B
REFERENCE
MAX1198
REFOUT REFN COM REFP REFIN
T/B PD SLEEP
Pin-Compatible Upgrades (Sampling Speed and Resolution)
8-BIT PART MAX1195 MAX1197 MAX1198 MAX1196* 10-BIT PART MAX1183 MAX1182 MAX1180 MAX1186 SAMPLING SPEED (Msps) 40 60 100 40, multiplexed
*Future product, please contact factory for availability.
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
48L,TQFP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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